COMPUTER ARCHITECTURE AND PARALLEL PROCESSING

 

A Section

 

Q1.Explain Flynn classifications of various computers based on notions of instructions and data streams.

Answer:

 

Q2 .What are static and dynamic networks of multiprocessor? Give two examples of both.

 

Q3 .Differentiate between RICS and CICS processors.     
 

   

Q4 .Explain nonlinear pipeline processor with suitable example.

 

Q5 .Differentiate between multiprocessors and multi-computers.

 

Answer


 

Section B

 

Case Study

 

ABC.com is a website where you can watch original movie DVDs.  It currently maitains the list of visitors and details of their visit.  The website gets almost 1 billion visitors everyday and at midnight it processes all the information.  It takes almost 5 hours to pocess all the information and the system remains down for that long. It causes the company a huge loss.  The company decided to buy a super computer for faster analysis. The supercomputer has 10 processors. Now the need is to design a parallel algorithm for the following problems:

 

We now have the list of visitors for the day and the number of movies they watched.

 

Q1. Design a parallel algorithm that would sort the names alphabetically. 

 

 

Q2. Now write a parallel search algorithm that would find a visitor "John" in this sorted list and show how many movies he watched. 

 

 

Q3. Can either sorting or searching achieve super linear speedup? 

 

C section

 

Question No.  1 Marks - 10 

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What was the period of third generation of electronics computers? 

  

Options

 

1. 1955-64 

 

2. 1965-74 

 

3. 1970-80 

 

4. 1975-90 

 

Question No.  2 Marks - 10 

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Which of the following is an example of shared memory multiprocessor models?

  

Options

 

1. Uniform Memory Access (UMA) 

 

2. Non-uniform Memory Access (NUMA) 

 

3. Cache Only Memory Access (COMA) 

 

4. All of the above.

 

Question No.  3 Marks - 10 

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Network latency refers to …

  

Options

 

1. The maximum data transfer rate in terms of M bytes/sec transmission through the network.

2. The worst-case time delay for a unite message to be transferred through the network.

3. Implementation cost such as those for wires, switches, connectors, arbitration etc.

4. The ability of the network to be modularly expandable with a scalable performance with increasing machine resource

 

Question No.  4 Marks - 10 

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Which of the following is an example of dynamic connection network?     

  

Options

 

1. Digital Bus 

 

2. Omega Network 

 

3. Crossbar Switch Network 

 

4. All of the above 

 

Question No.  5 Marks - 10 

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. VLIW stands for…

  

Options

 

1. Very Large Integration Word 

 

2. Very Long Integration Word 

 

3. Very Long Instruction Word 

 

4. Very Light Image Word 

 

Question No.  6 Marks - 10 

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Compiler used in implicit parallelism is…                                         

  

Options

 

1. Parallelizing compiler 

 

2. Concurrency preserving compiler 

 

3. Simple HLL compiler 

 

4. None of these. 

 

Question No.  7 Marks - 10 

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Number of nodes in the graph is called the…           

  

Options

 

1. In- degree 

 

2. Out- degree 

 

3. Total- degree 

 

4. Network size.

 

Question No.  8 Marks - 10 

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. Intel i960CA model is an example of….     

  

Options

 

1. CICS scalar processors 

 

2. RICS scalar processors 

 

3. Super scalar processors 

 

4. Vector processors 

 

Question No.  9 Marks - 10 

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Which of the following is an example of static connection network?                      

  

Options

 

1. 3-cube 

 

2. Switch- modules 

 

3. Systolic array 

 

4. a And c 

 

Question No.  10 Marks - 10 

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Paging and segmentation are associated to …

  

Options

 

1. Cache- memory 

 

2. Associative memory 

 

3. Virtual memory 

 

4. Volatile memory

 

Question No.  11 Marks - 10 

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In Distributed-Memory Multi-computers, each node is an autonomous computer consisting of a…….

  

Options

 

1. Processor 

 

2. Local Memory 

 

3. Attached Disk 

 

4. All of the above 

 

Question No.  12 Marks - 10 

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PRAM stands for…….

  

Options

 

1. Programmable Random Access Memory. 

 

2. Parallel Random Access Memory. 

 

3. Parallel Random Access Machine. 

 

4. None of the above. 

 

Question No.  13 Marks - 10 

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Synchronization of all PE’s in an SIMD computer is done by using…….

  

Options

 

1. Hardware 

 

2. Software 

 

3. Firmware 

 

4. Both a. and b.

 

Question No.  14 Marks - 10 

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. Parallelism can be achieved using …….

  

Options

 

1. Hardware 

 

2. Software 

 

3. Both hardware and software. 

 

4. It can not be achieved using hardware or software.

 

Question No.  15 Marks - 10 

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. Network routing algorithms could be ……

  

Options

 

1. Static only 

 

2. Dynamic only 

 

3. Both static and dynamic. 

 

4. Depends on network user. 

 

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Question No.  16 Marks - 10 

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Network scalability refers to ……

  

Options

 

1. The ability of a network to be modularly expandable with a scalable performance with increasing machine resources.

2. The machine data transfer rate, in terms of M bytes /s transmitted through the network.

3. The worst case time delay for a unit message to be transferred through the network.

4. Implementation costs such as those for wires, switches, connectors, arbitration and interface logic.

 

Question No.  17 Marks - 10 

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Base line network is an example of ….

  

Options

 

1. Static connection network. 

 

2. Dynamic connection network. 

 

3. It depends on the design. 

 

4. None of the above.

 

Question No.  18 Marks - 10 

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Crossbar network is an example of ……

  

Options

 

1. Static connection network. 

 

2. Dynamic connection network. 

 

3. It depends on the design. 

 

4. None of the above. 

 

Question No.  19 Marks - 10 

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Which of the following are speedup performance laws?

  

Options

 

1. Amdahl’s law for a fixed work load. 

 

2. Fixed –load speedup. 

 

3. Amdahl’s law revisited. 

 

4. All the above. 

 

Question No.  20 Marks - 10 

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Which of the following are scalability metrics?

  

Options

 

1. Machine size. 

 

2. Clock Rate. 

 

3. I/O demand 

 

4. All the above

 

Question No.  21 Marks - 10 

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. Instruction level parallelism could be achieved through……

  

Options

 

1. Instruction Pipelining. 

 

2. Vector Processing. 

 

3. Array Processing 

 

4. Multi Processor Architecture. 

 

Question No.  22 Marks - 10 

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. Which of the following is the fastest device in terms of speed?

  

Options

 

1. Cache Memory 

 

2. CPU Registers 

 

3. Main Memory 

 

4. Disk Storage 

 

Question No.  23 Marks - 10 

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Cache Locality of references refers to which of the following?

  

Options

 

1. Temporal Locality 

 

2. Sequential Locality 

 

3. Both a. and b. 

 

4. None of the above.

 

Question No.  24 Marks - 10 

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Cache hit ratio is?

  

Options

 

1. Number of times data found in cache / Total number of access. 

 

2. Number of times data not found in cache / total number of access. 

 

3. Number of times data found in RAM/ total number of access. 

 

4. Number of times data found in hard disk/ total number of access. 

 

Question No.  25 Marks - 10 

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Which techniques are examples of virtual memory?

  

Options

 

1. Demand paged memory management. 

 

2. Segmented memory management. 

 

3. Segmented paged memory management 

 

4. a and b. only.

 

Question No.  26 Marks - 10 

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Virtual memory could be achieved using which of the memory device?

  

Options

 

1. Cache memory 

 

2. Main memory 

 

3. CPU Register 

 

4. Secondary Memory 

 

Question No.  27 Marks - 10 

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Which is the fastest memory replacement technique?

  

Options

 

1. FCFS 

 

2. LRU 

 

3. OPT 

 

4. Depends on demand of size and order.

 

Question No.  28 Marks - 10 

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Which of the followings are cache addressing models?

  

Options

 

1. Physical address caches. 

 

2. Virtual address caches. 

 

3. Both a. and b. 

 

4. None of the above.

 

Question No.  29 Marks - 10 

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In which of the cache mapping scheme, word size of the cache is smallest?

  

Options

 

1. Direct mapping 

 

2. Associative mapping 

 

3. Set associative mapping 

 

4. In all the above cases, word size of the cache is same 

 

Question No.  30 Marks - 10 

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Cache coherence may occur in …..

  

Options

 

1. Multi-computer System. 

 

2. Multiprocessor Systems. 

 

3. Single Processor Systems. 

 

4. Both a. and b.

 

Question No.  31 Marks - 10 

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Cache coherence is the problem in which…..

  

Options

 

1. Duplicate data is in different caches of processors in multiprocessor systems.

2. Duplicate data in cache and in RAM. 

 

3. Duplicate data in cache, RAM and Hard Disk. 

 

4. All the above. 

 

Question No.  32 Marks - 10 

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Write-Through Caches applies the technique……

  

Options

 

1. Whenever there is modification in cache data, in main memory data modification will be finally once with same value which is finally modified in cache.

2. Whenever there is modification in cache data, simultaneously in main memory data modification will occur.

3. There is no relation of data modification of cache and main memory. 

 

4. It varies from processor to processor. 

 

Question No.  33 Marks - 10 

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Write-Back Cache applies the technique…….

  

Options

 

1. Whenever there is modification in cache data, in main memory data modification will be finally once with same value which is finally modified in cache.

2. Whenever there is modification in cache data, simultaneously in main memory data modification will occur.

3. There is no relation of data modification of cache and main memory. 

 

4. It varies from processor to processor. 

 

Question No.  34 Marks - 10 

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What is the basic unit in store-and-forward routing?

  

Options

 

1. Input/ Output stream. 

 

2. Packet. 

 

3. Byte. 

 

4. Message. 

 

Question No.  35 Marks - 10 

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Masking instruction is an instruction of which category?

  

Options

 

1. Pipeline Instruction 

 

2. Vector Instruction 

 

3. Scalar Instruction 

 

4. Array Instructions

 

Question No.  36 Marks - 10 

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DEC VAX 9000 is a….

  

Options

 

1. Mainframes. 

 

2. Mini Super Computer. 

 

3. Mini Computer. 

 

4. Multi Computer Architecture. 

 

Question No.  37 Marks - 10 

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Multi-pipelining could be achieved in ….

  

Options

 

1. Multi- Processor Systems. 

 

2. Multi-Computer System. 

 

3. Super Computer 

 

4. Mainframe

 

Question No.  38 Marks - 10 

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Label-1 cache may be in ….

  

Options

 

1. Inside processor chip. 

 

2. Outside processor chip and on board. 

 

3. A part of the RAM. 

 

4. A part of the hard disk.

 

Question No.  39 Marks - 10 

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Master-slave architecture is associated with…

  

Options

 

1. Multi-processor architecture. 

 

2. Multi-Computer architecture. 

 

3. Multi level cache coherence. 

 

4. All the above.

 

Question No.  40 Marks - 10 

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Using Flynn's taxonomy, the various architectures can be divided into categories.

  

Options

 

1. 3 

 

2. 4 

 

3. 5 

 

4. 6