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                                                                                                                   Digital Electronics & Computer Organisation

Sr. No may be change 

1 .What are flip flop circuits in digital electronics? Discuss race around condition in J-K Flip Flop.

2 .What is virtual memory? How address mapping is done in cache memory? Elaborate your answer with examples.        

3 .Design 8:1 Mux for a given function, f=Σ (0, 1,5,7,9, 13)

4 .How branching takes place in Instruction pipeline. Explain with suitable examples

5 .Write short notes on any three of the following.

  1. Microprocessor
  2. b)    Modes of data transfer.
  3. I/O processor
  4. Associative memory
  5. Software and Hardware interrupt

6 .Design a mod-15 counter. Explain the various steps in designing the counter

7. What are shift registers? Design a 8 bit shift register with features like PISO, SISO, SIPO and PIPO.

8 .Compare RISC & CISC architecture.



Assignment –B 

Case Detail:

  1. Give the organization of Micro programmed control unit and explain its operation. Explain the role of address sequencer in detail. If you convert your control unit to hardwired unit, what are the changes you will observe?

2. Explain in details the block diagram of timing and control unit.



Assignment –C

Question No.  1          

Where does a computer add and compare data?       


  1. Hard disk       
  2. Floppy disk    
  3. CPU chip      
  4. Memory chip


Question No.  2          

 Which of the following registers is used to keep track of address of the memory location where the next instruction is located?

  1. Memory Address Register     
  2. Memory Data Register           
  3. Instruction Register   
  4. Program Register


Question No.  3          

A complete microcomputer system consist of--                     

  1. microprocessor           
  2. memory          
  3. peripheral equipment  
  4. all of above


Question No.  4          

CPU does not perform the operation--          


  1. Data transfer
  2. Logic operation          
  3. Arithmetic operation  
  4. All of above


Question No.  5          

Pipelining strategy is called implement--                   

  1. Instruction execution 
  2. Instruction pre-fetch
  3. Instruction decoding  
  4. Instruction manipulation


Question No.  6          

 A stack is--


  1. An 8-bit register in the microprocessor          
  2. A 16-bit register in the microprocessor          
  3. A set of memory locations in R/WM reserved for storing information temporarily      
  4. A 16-bit memory address stored in the program counter


Question No.  7          

 . A stack pointer is--


  1. A 16-bit register in the microprocessor that indicate the beginning of the stack
  2. A register that decodes and executes 16-bit arithmetic expression   
  3. The first memory location where a subroutine address is stored.      
  4. A register in which flag bits are stored


Question No.  8          

The branch logic that provides decision making capabilities in the control unit is known as--


  1. Controlled transfer     
  2. Conditional transfer   
  3. Unconditional transfer        
  4. None of above


Question No.  9          

 Interrupts which are initiated by an instruction are--


  1. Internal           
  2. External          
  3. Hardware       
  4. Software


Question No.  10        

 A time sharing system imply--


  1. More than one processor in the system          
  2. More than one program in memory           
  3. More than one memory in the system
  4. None of above


Question No.  11        

 Processors of all computers, whether micro, mini or mainframe must have--


  1. ALU   
  2. Primary Storage         
  3. Control unit    
  4. All of above


Question No.  12        

What is the control unit´s function in the CPU?        


  1. To transfer data to primary storage    
  2. To store program instruction  
  3. To perform logic operations   
  4. To decode program instruction


Question No.  13        

What is meant by a dedicated computer?      


  1. Which is used by one person only?    
  2. Which is assigned to one and only one task?         
  3. Which does one kind of software?    
  4. Which is meant for application software only?


Question No.  14        

 The most common addressing techniques employed by a CPU is--


  1. Immediate      
  2. Direct 
  3. Indirect          
  4. Register
  5. All of the above        


Question No.  15        

 Pipeline implements--


  1. Fetch instruction        
  2. Decode instruction     
  3. Fetch operand
  4. Calculate operand
  5. All of above


Question No.  16        

 Which of the following code is used in present day computing was developed by

IBM Corporation?


  1. ASCII
  2. Hollerith Code           
  3. Baudot code  
  4. EBCDIC code


Question No.  17        

 When a subroutine is called, the address of the instruction following the CALL Instructions stored in/on the--


  1. Stack pointer  
  2. Accumulator  
  3. Program counter         
  4. Stack


Question No.  18        

 . A micro program written as string of 0´s and 1´s is a--


  1. Symbolic microinstruction     
  2. Binary microinstruction         
  3. Symbolic micro program        
  4. Binary micro program


Question No.  19        

 Memory access in RISC architecture is limited to instructions--


  1. CALL and RET         
  2. PUSH and POP         
  3. STA and LDA          
  4. MOV and JMP


Question No.  20        

 . A collection of 8 bits is called--


  1. Byte   
  2. Word  
  3. Record
  4. Code


Question No.  21        

An AND gate generates a high output when--


  1. Any one of its inputs is high  
  2. All of its inputs are high      
  3. When all of its inputs are low
  4. Power fails


Question No.  22        

 How many address lines are needed to address each memory locations in a

         2048 x 4 memory chip?


  1. 10       
  2. 11       
  3. 8         
  4. 12


Question No.  23        

 . A computer program that converts an entire program into machine language at

        One time is called a/an--


  1. Interpreter      
  2. Simulator        
  3. Compiler       
  4. Commander


Question No.  24        

 In immediate addressing the operand is placed--


  1. In the CPU register    
  2. After OP code in the instruction     
  3. In memory      
  4. In stack


Question No.  25        

 Microprocessor 8085 can address location up to--


  1. 32K    
  2. 128K  
  3. 64K    
  4. 1M


Question No.  26        

 The ALU and control unit of most of the microcomputers are combined and manufactured on a single silicon chip. What is it called?


  1. Mono chip      
  2. Microprocessor         
  3. ALU   
  4. Control unit    


Question No.  27        

When the RET instruction at the end of subroutine is executed,      


  1. The information where the stack is initialized is transferred to the stack pointer     
  2. The memory address of the RET instruction is transferred to the program counter 
  3. Two data bytes stored in the top two locations of the stack are transferred to the program counter           
  4. Two data bytes stored in the top two locations of the stack are transferred to the stack pointer     


Question No.  28        

A micro program is sequencer perform the operation--         


  1. Read   
  2. Write  
  3. Execute          
  4. Read and write
  5. Read and execute     


Question No.  29        

Interrupts which are initiated by an I/O drive are--   


  1. Internal           
  2. External        
  3. Software        
  4. All of above


Question No.  30        

 A 32-bit processor has--


  1. 32 registers     
  2. 32 I/O devices
  3. 32 Mb of RAM          
  4. 32-bit bus or 32-bit registers


Question No.  31        

Clock speed is measured in-- 


  1. Bits per second          
  2. Baud  
  3. Bytes  
  4. Hertz


Question No.  32         Marks - 10

 A parity bit is--


  1. Used to indicate uppercase letters     
  2. Used to detect errors
  3. Is the first bit in a byte?         
  4. Is the last bit in a byte?


Question No.  33        

 On-chip cache has--


  1. Lower access time than RAM         
  2. Larger capacity than off chip Cache  
  3. Its own data bus        
  4. Become obsolete


Question No.  34        

 The system bus is made up of--


  1. Data bus         
  2. Data bus and address bus      
  3. Data bus and control bus       
  4. Data bus, control bus and address bus


Question No.  35        

Modern processor chips may be classified as--          


  1. LSI     
  2. ULSI  
  3. MIPS  
  4. SSI


Question No.  36        

A nanosecond is--      


  1. 10-6 sec          
  2. 10-3 sec          
  3. 10-12 sec        
  4. 10-9 sec


Question No.  37        

The clock speed of a modern PC is of the order of--


  1. 400 KHz        
  2. 400 Hz
  3. 400 MHz        
  4. 400 Ghz


Question No.  38        

An OR gate generates a low output when--


  1. Any one of its inputs is low   
  2. All of its inputs are high        
  3. When all of its inputs are low          
  4. Power fails


Question No.  39        

The ascending order or a data Hierarchy is--


  1. bit - bytes - fields - record - file - database 
  2. bit - bytes - record - field - file - database     
  3. bytes - bit- field - record - file - database      
  4. bytes -bit - record - field - file – database


Question No.  40

A conditional jump instruction-


  1. Always cause a transfer of control 
  2. Always involves the use of the status register           
  3. Always modifies the program counter           
  4. Always involves testing the Zero flag  
  Answers :-

                                                                                                          Digital Electronics & Computer Organisation


1 .What are flip flop circuits in digital electronics? Discuss race around condition in J-K Flip Flop.


In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bitable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.

Digital Electronics: Types of Flip-Flop Circuits?

By Doug Lowe from Electronics All-in-One for Dummies

In electronics, a flip-flop is a special type of gated latch circuit. There are several different types of flip-flops. The most common types of flip flops are:

  • SR flip-flop: Is similar to an SR latch. Besides the CLOCK input, an SR flip-flop has two inputs, labeled SET and RESET. If the SET input is HIGH when the clock is triggered, the Q output goes HIGH. If the RESET input is HIGH when the clock is triggered, the Q output goes LOW.

Note that in an SR flip-flop, the SET and RESET inputs shouldn´t both be HIGH when the clock is triggered. This is considered an invalid input condition, and the resulting output isn´t predictable if this condition occurs.

  • D flip-flop: Has just one input in addition to the CLOCK input. This input is called the DATA input. When the clock is triggered, the Q output is matched to the DATA input. Thus, if the DATA input is HIGH, the Q output goes HIGH, and if the DATA input is LOW, the Q output goes LOW.

Most D-type flip-flops also include S and R inputs that let you set or reset the flip-flop. Note that the S and R inputs in a D flip-flop ignore the CLOCK input. Thus, if you apply a HIGH to either S or R, the flip-flop will be set or reset immediately, without waiting for a clock pulse.

  • JK flip-flop: A common variation of the SR flip-flop. A JK flip-flop has two inputs, labeled J and The J input corresponds to the SET input in an SR flip-flop, and the K input corresponds to the RESET input.

The difference between a JK flip-flop and an SR flip-flop is that in a JK flip-flop, both inputs can be HIGH. When both the J and K inputs are HIGH, the Q output is toggled, which means that the output alternates between HIGH and LOW.

For example, if the Q output is HIGH when the clock is triggered and J and K are both HIGH, the Q output is set to LOW. If the clock is triggered again while J and K both remain HIGH, the Q output is set to HIGH again, and so forth, with the Q output alternating from HIGH to LOW at every clock tick.

  • T flip-flop: Thisis simply a JK flip-flop whose output alternates between HIGH and LOW with each clock pulse. Toggles are widely used in logic circuits because they can be combined to form counting circuits that count the number of clock pulses received.

You can create a T flip-flop from a D flip-flop by connecting the Q-bar output directly to the D input. Thus, whenever a clock pulse is received, the current state of the Q output is inverted (that’s what the Q-bar output is) and fed back into the D input. This causes the output to alternate between HIGH and LOW.

Race condition

An error condition in which two signals or sets of data collide. It can take place within a chip, a circuit, a network or an application. It can be due to a timing malfunction in the hardware or poorly written software.

Race Condition and Race around condition are different.

Race Condition only means that the input signals are in race to change the output. This may be due to the difference in propagation or routing delays in the signal paths. This results in glitches, but the circuit will be stable.

Race around condition is different and is very undesirable. It usually occurs when the output triggers a change in output. This occurs in systems where output is feedback. A change in output may change the output again and again before it settles..... Making the output indeterminate. This is Race Around condition. It makes the circuit unstable. This racing around (output is in race to change output) condition is called Race around condition

J-K Flip Flop in Digital Electronics

This is Part 4 in a series on Flip Flops in Digital Electronics. The full series is Part 1, Part 2, Part 3, Part 4, Part 5 and Part 6.

The J-K Flip Flop has two data inputs J & K, a single clock input and two outputs Q and Q’. J-K Flip Flop is used to avoid the forbidden state of S-R Flip Flop.

Let Qn and Qn+1 represent the present state and next state of the flip flop, here is the truth table and circuit diagram of a J-K Flip Flop

























































When J=1, K=1, the Q output will be in the Qn’ state after clocking i.e. Qn+1=Qn’. This is known as toggling. The flip flop will complement itself each time the circuit switches from high to low. The flip flop is said to toggle.

Race-Around Condition in J-K Flip Flop

Practically, we don’t get toggling. Since, clock pulse is more than the propagation delay, so within one clock pulse the output will keep on toggling again and again and it may become indeterminate. This is known as race around condition. Race Around condition occurs because of the feedback connection.

There are three ways to avoid Race-Around Condition:

  1. If Ton < Tpd

I.e. clock pulse is less than the propagation delay. Practically Tpd is of the order of nanoseconds or picoseconds and therefore, it is only a theoretical possibility to get clock pulse lower than propagation delay.

  1. Another way is by using Edge Triggering

In edge triggering output is affected only at the time of presence of edge i.e. only during the rising or falling edge of a clock pulse. When the input clock pulse makes a +ve going transition (or a -ve going transition), the value of input is transferred to output i.e. Q. Changes in input when clock is maintained at a steady 1 value do not affect Q. Moreover, a -ve pulse transition does not affect the output and nor does when clock pulse is 0. Hence the edge triggered flip flop eliminates any feedback problem in sequential circuit.

  1. By using Master-Slave Flip Flop

Read the full series at Part 1, Part 2, Part 3, Part 4, Part 5 and Part 6.


2 .What is virtual memory? How address mapping is done in cache memory? Elaborate your answer with examples.       


In computing, virtual memory is a memory management technique that is implemented using both hardware and software. It maps memory addresses used by a program, called virtual addresses, into physical addresses in computer memory. Main storage as seen by a process or task appears as a contiguous address space or collection of contiguous segments. The operating system manages virtual address spaces and the assignment of real memory to virtual memory. Address translation hardware in the CPU, often referred to as a memory management unit or MMU, automatically translates virtual addresses to physical addresses. Software within the operating system may extend these capabilities to provide a virtual address space that can exceed the capacity of real memory and thus reference more memory than is physically present in the computer.

The primary benefits of virtual memory include freeing applications from having to manage a shared memory space, increased security due to memory isolation, and being able to conceptually use more memory than might be physically available, using the technique of paging.

Cache memory

The cache is a small amount of high-speed memory, usually with a memory cycle time comparable to the time required by the CPU to fetch one instruction. The cache is usually filled from main memory when instructions or data are fetched into the CPU. Often the main memory will supply a wider data word to the cache than the CPU requires, to fill the cache more rapidly. The amount of information which is replaces at one time in the cache is called the line size for the cache. This is normally the width of the data bus between the cache memory and the main memory. A wide line size for the cache means that several instruction or data words are loaded into the cache at one time, providing a kind of prefetching for instructions or data. Since the cache is small, the effectiveness of the cache relies on the following properties of most programs:

  • Spatial locality -- most programs are highly sequential; the next instruction usually comes from the next memory location.

Data is usually structured, and data in these structures normally are stored in contiguous memory locations.

  • Short loops are a common program structure, especially for the innermost sets of nested loops. This means that the same small set of instructions is used over and over.

Generally, several operations are performed on the same data values, or variables

If the particular address is found in the cache, theblock of data is sent to the CPU, and the CPU goes aboutits operation until it requires something else frommemory. When the CPU finds what it needs in thecache, a hit has occurred. When the address requestedby the CPU is not in the cache, a miss has occurred andthe required address along with its block of data isbrought into the cache according to how it is mapped.Cache processing in some computers is divided intotwo sections: main cache and eavesdrop cache. Maincache is initiated by the CPU within. Eavesdrop is donewhen a write to memory is performed by anotherrequestor (other CPU or IOC). Eavesdrop searcheshave no impact on CPU performances.


Cachemapping is the method by which the contents of mainmemory are brought into the cache and referenced bythe CPU. The mapping method used directly affects theperformance of the entire computer system..

  1. Direct mapping—Main memory locations canonly be copied into one location in the cache. This isaccomplished by dividing main memory into pages thatcorrespond in size with the cache (fig. 5- 10).
  2. Fully associative mapping —Fully associativecache mapping is the most complex, but it is mostflexible with regards to where data can reside. A newlyread block of main memory can be placed anywhere ina fully associative cache.

A direct mapped cache configuration

This was, in fact, the way the cache is organized in the PDP-11/60. In the 11/60, however, there are 4 other bits used to ensure that the data in the cache is valid. 3 of these are parity bits; one for each byte and one for the tag. The parity bits are used to check that a single bit error has not occurred to the data while in the cache. A fourth bit, called the valid bit is used to indicate whether or not a given location in cache is valid. In the PDP-11/60 and in many other processors, the cache is not updated if memory is altered by a device other than the CPU (for example when a disk stores new data in memory). When such a memory operation occurs to a location which has its value stored in cache, the valid bit is reset to show that the data is ``stale´´ and does not correspond to the data in main memory. As well, the valid bit is reset when power is first applied to the processor or when the processor recovers from a power failure, because the data found in the cache at that time will be invalid.

In the PDP-11/60, the data path from memory to cache was the same size (16 bits) as from cache to the CPU. (In the PDP-11/70, a faster machine, the data path from the CPU to cache was 16 bits, while from memory to cache was 32 bits which means that the cache had effectively perfected the next instruction, approximately half of the time). The amount of information (instructions or data) stored with each tag in the cache is called the line size of the cache. (It is usually the same size as the data path from main memory to the cache.) A large line size allows the prefetching of a number of instructions or data words. All items in a line of the cache are replaced in the cache simultaneously, however, resulting in a larger block of data being replaced for each cache miss.



3 .Design 8:1 Mux for a given function, f=Σ (0, 1,5,7,9, 13)


4 .How branching takes place in Instruction pipeline. Explain with suitable examples


Pipelining is a key implementation technique used to build fast processors. It allows the execution of multiple instructions to overlap in time.

A pipeline within a processor is similar to a car assembly line. Each assembly station is called a pipe stage or a pipe segment.

The throughput of an instruction pipeline is the measure of how often an instruction exits the pipeline.

An instruction pipeline is a technique used in the design of computers to increase their instruction throughput (the number of instructions that can be executed in a unit of time). The basic instruction cycle is broken up into a series called a pipeline. Rather than processing each instruction sequentially (one at a time, finishing one instruction before starting the next), each instruction is split up into a sequence of steps – different steps can be executed concurrently (by different circuitry), and indeed in parallel (at the same time).

Each instruction is split into a sequence of dependent steps. The first step is always to fetch the instruction from memory; the final step is usually writing the results of the instruction to processor registers or to memory. Pipelining seeks to let the processor work on as many instructions as there are dependent steps, just as an assembly line builds many vehicles at once, rather than waiting until one vehicle has passed through the line before admitting the next one. Just as the goal of the assembly line is to keep each assembler productive at all times, pipelining seeks to keep every portion of the processor busy with some instruction. Pipelining lets the computer´s cycle time be the time of the slowest step, and ideally lets one instruction complete in every cycle.

Pipeline Stages

We can divide the execution of an instructioninto the following 5 “classic” stages:

            IF: Instruction Fetch

            ID: Instruction Decode, register fetch

            EX: Execution

            MEM: Memory Access

            WB: Register write back



A branch out of the normal instruction sequence often involves a hazard. Unless the processor can give effect to the branch in a single time cycle, the pipeline will continue fetching instructions sequentially. Such instructions cannot be allowed to take effect because the programmer has diverted control to another part of the program.

A conditional branch is even more problematic. The processor may or may not branch, depending on a calculation that has not yet occurred. Various processors may stall, may attempt branch prediction, and may be able to begin to execute two different program sequences (eager execution), both assuming the branch is and is not taken, discarding all work that pertains to the incorrect guess.[a]

A processor with an implementation of branch prediction that usually makes correct predictions can minimize the performance penalty from branching. However, if branches are predicted poorly, it may create more work for the processor, such as flushing from the pipeline the incorrect code path that has begun execution before resuming execution at the correct location.

Programs written for a pipelined processor deliberately avoid branching to minimize possible loss of speed. For example, the programmer can handle the usual case with sequential execution and branch only on detecting unusual cases. Using programs such as gcov to analyze code coverage lets the programmer measure how often particular branches are actually executed and gain insight with which to optimize the code










Sign extend














Reduction of Branch Penalties

Static, compile-time, branch prediction schemes

1   Stall the pipeline

                        Simple in hardware and software

2 Treat every branch as not taken

               Continue execution as if branch were normal instruction

                If branch is taken, turn the fetched instruction into a no-op

3 Treat every branch as taken

               Useless in MIPS …. Why?

4   Delayed branch

                Sequential successors (in delay slots) are executed anyway

                No branches in the delay slots

Branch Slot Requirements



Improves performance


a) From before

Branch must not depend on delayedinstruction



b) From target

Must be OK to execute delayedinstruction if branch is not taken

When branch is taken


c) From fallthrough    

Must be OK to execute delayedinstruction if branch is taken           

When branch is not taken




5 .Write short notes on any three of the following.


  1. Microprocessor


A siliconchip that contains a CPU. In the world of personal computers, the terms microprocessor and CPU are used interchangeably. At the heart of all personal computers and most workstations sits a microprocessor. Microprocessors also control the logic of almost all digitaldevices, from clock radios to fuel-injection systems for automobiles.

Three basic characteristics differentiate microprocessors:

Instruction set: The set of instructions that the microprocessor can execute.

Bandwidth: The number of bits processed in a single instruction.

Clock speed: Given in megahertz (MHz), the clock speed determines how many instructions per second the processor can execute.

In both cases, the higher the value, the more powerful the CPU. For example, a 32-bit microprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that runs at 25MHz

12-bit designs

The Intersex 6100 family consisted of a 12-bit microprocessor (the 6100) and a range of peripheral support and memory ICs. The microprocessor recognized the DEC PDP-8minicomputer instruction set. As such it was sometimes referred to as the CMOS-PDP8. Since it was also produced by Harris Corporation, it was also known as the Harris HM-6100. By virtue of its CMOS technology and associated benefits, the 6100 was being incorporated into some military designs until the early 1980s.

16-bit designs

The first multi-chip 16-bit microprocessor was the National SemiconductorIMP-16, introduced in early 1973. An 8-bit version of the chipset was introduced in 1974 as the IMP-8.

Other early multi-chip 16-bit microprocessors include one that Digital Equipment Corporation (DEC) used in the LSI-11 OEM board set and the packaged PDP 11/03minicomputer—and the Fairchild SemiconductorMicro Flame 9440, both introduced in 1975–1976. In 1975, National introduced the first 16-bit single-chip microprocessor, the National Semiconductor PACE, which was later followed by an NMOS version, the INS8900.

32-bit design

16-bit designs had only been on the market briefly when 32-bit implementations started to appear.

The most significant of the 32-bit designs is the Motorola MC68000, introduced in 1979. The 68k, as it was widely known, had 32-bit registers in its programming model but used 16-bit internal data paths, three 16-bit Arithmetic Logic Units, and a 16-bit external data bus (to reduce pin count), and externally supported only 24-bit addresses (internally it worked with full 32 bit addresses). In PC-based IBM-compatible mainframes the MC68000 internal microcode was modified to emulate the 32-bit System/370 IBM mainframe

64-bit designs in personal computer

While 64-bit microprocessor designs have been in use in several markets since the early 1990s (including the Nintendo 64gaming console in 1996), the early 2000s saw the introduction of 64-bit microprocessors targeted at the PC market.


  1. b) Modes of data transfer.


Modes of transfer

Three Possible mode:

Data transfer between central computer and I/O devices may be handles in a variety of modes. The three possible modes are

  1. Programmed I/O
  2. Interrupt-initiated I/O
  3. Direct Memory Access (DMA)


  1. Programmed I/O Mode:-

-> In programmed I/O mode data are exchanged between the processor and the I/O module. When a processor is executing a program and encounters an instruction relating to I/O, it executes that instruction by issuing a command to that appropriate I/O module. With programmed I/O the I/O module will perform the requested action and then set the appropriate bit in the I/O status register.

-> The I/O module takes no further action to alert the processor (it doesn’t interrupt the processor).

-> The I/O commands issued by the processor to the I/O module

  • Test
  • Control
  • Read
  • Write
  1. Memory Mapped I/O:-

->There is a single address space for memory location and I/O devices.( the address space is shared)

->With memory mapped I/O a single read line a single write line are needed on the bus. The bus may be equipped with memory read and write plus Input and output command lines.

->Now the command lines specifies whether the address refers to memory location or an I/O device.

->Most CPU uses memory mapped I/O.

-> Always CPU assigns address to memory some of memory space is stolen and assigned to I/O device.

->It deals with fewer address lines.

  1. Interrupt Driven I/O:-

->In this method the program issues an I/O command and then continues to execute until it is interrupted by the I/O hardware to signal the end of I/O operation.

-> Here the program enters a wait loop in which it repeatedly checks the device status. During this process the processor is not performing any useful computation.

->There are many situations where tasks can be performed while waiting for an I/O device to be ready, to allow this the I/O device should alert the processor when it becomes ready. It can be done by sending a hardware signal called an interrupt.

->The routine executed in response to an interrupt request is called Interrupt Service Routine (ISR).

->The processor first completes execution of instruction then it loads the program counter (pc) with the address of 1st instruction of ISR.

4. Direct Memory Access:-

->In this method the input and output devices read/write information from the main memory without interference of the CPU through the system bus.

-> For I/O transfer, processor determines the status of I/O by:

  • Polling
  • Waiting for interrupt signal.

->Considerable Overhead is incurred in above I/O transfer processing.

->By DMA approach, large blocks of data at high speed can be sent between external device and main memory.


  1. c) I/O processor


Input/Output processor (IOP)

The IOP attaches to the system I/O bus and one or more input/output adapters (IOAs). The IOP processes instructions from the system and works with the IOAs to control the I/O devices.

There are many different kinds of IOPs.

  • Some IOPs can only support one type of I/O device. In this case the IOA is embedded in the IOP so you cannot remove the IOA or change it.
  • Some IOPs can support multiple device types, but only one at a time. The type of IOA that is attached determines what device can be used. IOAs on these IOPs can be changed with another IOA to support a different I/O device.
  • Some IOPs can support multiple types of I/O devices at the same time. These are known as MFIOPs or CFIOPs (this depends on the type of IOP). IOAs for the supported types of I/O devices attach to the IOP.

There are several important I/O devices in the system. These include the load source disk unit, the alternate IPL device, the console, and the electronic customer support hardware. The system needs to know where to locate these special devices on secondary partitions. When you create a logical partition, you need to identify the IOPs that control these important devices:

In computer science, channel I/O is a high-performance input/output (I/O) architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers. In the past they were generally implemented with a custom processor, variously named channel,peripheral processor, I/O processor, I/O controller, or DMA controller


Many I/O tasks can be complex and require logic to be applied to the data to convert formats and other similar duties. In these situations, the simplest solution is to ask the CPU to handle the logic, but because I/O devices are relatively slow, a CPU could waste time (in computer perspective) waiting for the data from the device. This situation is called ´I/O bound´.

Channel architecture avoids this problem by using a separate, independent, low-cost processor. Channel processors are simple, but self-contained, with minimal logic and sufficient on-board scratchpad memory (working storage) to handle I/O tasks. They are typically not powerful or flexible enough to be used as a computer on their own and can be construed as a form of coprocessor.

A CPU sends relatively small channel programs to the controller via the channel to handle I/O tasks, which the channel and controller can, in many cases, complete without further intervention from the CPU (exception: those channel programs which utilize ´program controlled interrupts´, PCIs, to facilitate program loading, demand paging and other essential system tasks).

When I/O transfer is complete or an error is detected, the controller communicates with the CPU through the channel using an interrupt. Since the channel has direct access to the main memory, it is also often referred to as DMA controller (where DMA stands for direct memory access), although that term is looser in definition and is often applied to non-programmable devices as well


  1. d) Associative memory


Associative memory may refer to:


  1. e) Software and Hardware interrupt


In system interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention .the processor responds by suspending its current activities, saving its state and executing a small program called an interrupt handler to deal with the event.

Hardware interrupt

This interrupt is caused by some external device such as request to start an i/o or occurrence of a hardware failure.

A hardware interrupt is an electronic alerting signal sent to the processor from an external device, either a part of the computer itself such as a disk controller or an external peripheral. For example pressing a key on the keyboard or moving the mouse triggers hardware interrupt that cause the processor to read the keystroke or mouse position. The act of initiating a hardware interrupt is referred to as an interrupt request.

Software interrupt

Is caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed. The former is often called a trap or exception and is used for errors or events occurring during program execution that are exceptional enough that they cannot be handled within the program itself. For example if the processors arithmetic logic unit is commanded to divide a number by zero, this impossible demand will cause a divide by zero exception ,perhaps causing the computer to abandon the calculation or display an error message.


6 .Design a mod-15 counter. Explain the various steps in designing the counter


Counters are sequential circuits that cyclethrough some states.

  • They can be implemented using flip-flops.
  • Implementation is simple: using T flip-flops(with toggle output) or with anyother flip-flops that can be connected togive the required function



  • Are available in two categories
    1. Ripple counters (Asynchronous)

The flip-flop output transition serves as a source for triggering other flip-flops i.e. the C input of some or all flip-flops are triggered NOT by the common clock pulses

Eg: - Binary ripple counters

BCD ripple counters

Ripple counters

  • Use complemented flip flop


Binary Ripple up counter

  • Consist of a series of connection of negative edge triggering complementing flip-flops with the

Output of each flip-flop connected to the C input of the next high order flip flop

The flip flop holding the LSB receives the input pulses.

  • The count starts with binary 0 and increments by one with each count pulse input
  • After the count 15 the counter goes back to binary 0 to repeat the count


BCD Ripple Counter, Decade counter

This counter counts upwards on each negativeedge of the input clock signal starting from "0000"until it reaches an output "1001“. Both outputs QAand QD are now equal to logic "1" and the outputfrom the NAND gate changes state from logic"1" to a logic "0" level when the clock goes to level one and whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flip-flops


Decade Counter Timing Diagram




  1. Synchronous counters

The C inputs of all flip-flops receive the common clock pulses

E.g.:-Binary counter

Up-down Binary counter

BCD Binary counter

Ring counter

Johnson counter


Binary Synchronous Counter

The FF in the LSB is complemented with every pulse. A flip flop in other position is complemented when all the bits in the lower significant positions are 1

  • Synchronous counter have a regular pattern and can be constructed with complementing flip flops and gates


Up-Down Binary Counters

  • It can progress in either direction (up or down)

0 1 2 3 4 5 4 3 2 3 4 5 6 76 5 etc...

up dn up dn

The countdown counter can be constructed as follows, the inputs to the AND gates must come from the complement outputs instead of the normal outputs of the previous flip flops.

The Up and down counters can be combined in one circuit to form a counter capable of counting either up or down.

Binary Counter with Parallel Load

  • It can be loaded with initial value to start counting


Binary Counter with Parallel Load



Ring counters

  • An n-bit ring counter cycles through n states. The single bit is shifted from one flip flop to the next in order to generate unique timing signals


Johnson Counters

  • An n-bit Johnson counter (also called switch tail ring counter) cycles through 2n states.
  • Example: A 4-bit John counter (also called mod-8 Johnson counter)





  1. Determine the # of FFs needed to support the counting sequence’s highest #. 2n -1 ≥ Highest #


  1. Determine what states you want to toggle FROM 􀃆TO. Example:

0 􀃆5

000 􀃆101

  1. Build a truth Table.


  1. Simplify logic using a K-Map.


  1. Implement the design on the basic Asynchronous Counter Circuit.


  1. Draw the Timing Diagram (If Needed



  1. Determine the # of FFs needed to support the counting sequences

Highest #.2n -1 ≥ Highest #

  1. Build a State Transition Diagram. Be sure to include all states.
  2. Build a State/Excitation Truth Table.
  3. Simplify expressions for J and K inputs for each F/F on K-Maps.
  4. Implement the Synchronous Counter/State Machine Circuit.
  5. Draw the Timing Diagram (If Needed).




0 􀃆0 0 X

0 􀃆1 1 X

1 􀃆0 X 1

1 􀃆1 X 0


  1. What are shift registers? Design a 8 bit shift register with features like PISO, SISO, SIPO and PIPO.


In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its input and shifting out the last bit in the array, at each transition of the clock input. More generally, a shift register may be multidimensional, such that it’s "data in" and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are often configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are also bi-directional shift registers which allow shifting in both directions: L→R or R→L. The serial input and last output of a shift register can also be connected to create a circular shift register.

Destructive readout





































These are the simplest kind of shift registers. The data string is presented at ´Data In´, and is shifted right one stage each time ´Data Advance´ is brought high. At each advance, the bit on the far left (i.e. ´Data In´) is shifted into the first flip-flop´s output. The bit on the far right (i.e. ´Data Out´) is shifted out and lost.

The data are stored after each flip-flop on the ´Q´ output, so there are four storage ´slots´ available in this arrangement, hence it is a 4-Bit Register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As ´Data In´ presents 1, 0,1,1,0,0,0,0 (in that order, with a pulse at ´Data Advance´ each time—this is called clocking or strobing) to the register, this is the result. The left hand column corresponds to the left-most flip-flop´s output pin, and so on.

So the serial output of the entire register is 10110000. It can be seen that if data were to be continued to input, it would get exactly what was put in, but offset by four ´Data Advance´ cycles. This arrangement is the hardware equivalent of a queue. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high.

This arrangement performs destructive readout - each datum is lost once it has been shifted out of the right-most bit.

Serial-in, parallel-out (SIPO)


This configuration allows conversion from serial to parallel format. Data is input serially, as described in the SISO section above. Once the data has been inputted, it may be either read off at each output simultaneously, or it can be shifted out and replaced.

In cases where the parallel outputs should not change during the serial loading process, it is desirable to use a latched output. In a latched shift register (such as the 74595) the serial data is first loaded into an internal shift register, then upon receipt of a load signal the state of the shift register is copied into a set of output registers. In general, the practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires.

Parallel-in, Serial-out (PISO

This configuration has the data input on lines D1 through D4 in parallel format, being D1 the MSB. To write the data to the register, the Write/Shift control line must be held LOW. To shift the data, the W/S control line is brought HIGH and the registers are clocked. The arrangement now acts as a SISO shift register, with D1 as the Data Input. However, as long as number of clock cycles is not more than the length of the data-string, the Data Output, Q, will be the parallel data read off in order.

4-Bit PISO Shift Register

The animation below shows the write/shift sequence, including the internal state of the shift register.


8 .Compare RISC & CISC architecture.


Layman terms, computers can be defined as a hierarchical series of metal, silicon and plastic (Hardware) fused with software all around it. These two entities combine to form a powerful machine that can process gigabytes of data in a span of a few seconds. The role played by hardware and software has always been closely studied so as to find which one should play the major part. Major Computer manufacturing firms Apple and Intel have always been arguing on importance of hardware and software in CPU architecture designs. Intel supporters want the hardware to bear more responsibility and software on the easier side. This would impact the hardware designin


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